The present invention relates to a semiconductor device, in particular, a technology effective when applied to a semiconductor device including a fin transistor.
A fin transistor is known as a field effect transistor which has a high operating rate, can be operated with a reduced leakage current at reduced energy consumption, and can be downsized. A fin transistor (FINFET: fin field effect transistor) is, for example, a semiconductor element having, as a channel layer, a plate-like (wall-like) semiconductor layer pattern protruding from a semiconductor substrate and having a gate electrode formed so as to stride over the pattern.
As an electrically programmable and erasable nonvolatile semiconductor memory device, EEPROM (electrically erasable and programmable read only memory) has been used widely. Such a memory device typified by a flash memory which is popularly used now has, below the gate electrode of its MISFET, a conductive floating gate electrode or trapping insulating film surrounded by an oxide film. It uses, as stored formation, a charge accumulation state in the floating gate or trapping insulating film and reads it out as the threshold of the transistor. This trapping insulating film means an insulating film in which charges can be accumulated and one example of it is a silicon nitride film. The flash memory is operated as a memory element by injecting or releasing charges into or from such a charge accumulation region and thereby shifting the threshold of the MISFET. Examples of this flash memory include a split-gate cell using a MONOS (metal-oxide-nitride-oxide-semiconductor) film.
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2006-041354 describes a split-gate MONOS memory comprised of a FINFET.